This application claims the priority benefit of Taiwan application serial no. 89101270, filed Jan. 26, 2000.
1. Field of Invention
The present invention relates to a signal delay device and a method of calibrating the delay period. More particularly, the present invention relates to a signal delay device having an internal delay lock loop for calibrating the delay interval.
2. Description of Related Art
Due to the rapid progress in semiconductor technologies, computational capability of a computer increases at a tremendous pace. At present, most computers are constructed using digital circuits. Synchronization among various internal devices is achieved using one or more reference clock signals such that various devices cooperate each other. In earlier computer system, data can be easily transferred among internal devices because the operating speed is low.
FIG. 1 illustrates a conventional timing diagram of data transmission using a clock. In FIG. 1, signal DAT represents transmission data and signal CLK represents the waveform of a system clock. Since the data signal DAT varies according to the clock signal CLK, the receiving terminal of a device is able to receive the data signal correctly. However, this method is only suitable for the transmission of data in earlier operating system. As the operating frequency of a system increases, precision of data transmission is difficult to maintain in the same way so as to lead to many possible system problems.
FIG. 2 illustrates a circuit block diagram of a conventional data transmission system using a clock signal. As shown in FIG. 2, a transmission device 210 transmits data signals DAT to a receiving device 220 through a transmission line 230. During transmission, signal is delayed due to the buffer 214 inside the transmission device 210, the buffer 224 inside the receiving device 220 and the transmission line 230 (flight time). In addition, the flip-flop 212 inside the transmission device 210 and the flip-flop 222 inside the receiving device 220 both use the clock signal CLK to latch-up the data. The clock signal CLK propagating through the transmission line 240 results in clock skew due to the delay in the circuit. In an actual digital system, there can be a total signal delay of 2xcx9c3 ns (nano-second) from the transmitting terminal to the receiving terminal. Due to the above consideration, data holding time on data line must be extended for accurate transmission of data through the circuit. Inconsequence, it is difficult to raise clock frequency and data transmission rate.
To reduce clock delay and data loss problem during data transmission, data strobe signals are introduced. FIG. 3A illustrates a circuit block diagram of a conventional data transmission system with data strobe. FIG. 3B illustrates a timing diagram showing data strobe and data line waveform. As shown in FIG. 3A, the flip-flop 316 inside the transmission device 310 converts a clock signal CLK into a data strobe signal DS. Data signal DAT is sent accompanied by the data strobe signals DS. The flip-flop 322 inside the receiving device 320 receives data according to the data strobe signal DS. Hence, delay Tbuffer for the buffers and flight time on the transmission line Tflight are eliminated. Furthermore, both the rising edge and the falling edge of the data strobe signal DS can be used for data transmission. In other words, the system is capable of operation in a double data rate (DDR) mode, for example, in DDR SDRAM (synchronous dynamic random access memory). If skew of the data strobe signal DS between the transmission terminal and the receiving terminal can be disregarded, transmission speed is limited by the setup and hold time of the flip-flop 322 inside the receiving device 320 only. In general, the setup time is about 0.5 ns and hold time is about 0.5 ns.
In real applications, data signal DAT and data strobe signal DS are generated and transmitted from the transmission terminal synchronously. In other words, data signal DAT and data strobe signal DS are transmitted from the transmitting terminal at the rising or falling edge of a clock signal. By having the same delay trace, delay time Tbuffer of the buffers and delay time Tflight of the transmission line are balanced, and skew between the data signal DAT and data strobe signal DS is minimized. Timing sequence of the signal transmission is shown in FIG. 3B. However, since data access is carried out at the rising edge or falling edge of a data strobe signal DS, the data strobe signal DS must be delayed for a period of time at the receiving device 320 to ensure data accuracy.
FIG. 4A illustrates a block diagram showing the addition of a data delay element at the receiving terminal of a conventional data transmission system. FIG. 4B illustrates a timing diagram of data strobe signal, data signal and delayed data strobe signal. As shown in FIGS. 4A and 4B, the rising edge and the falling edge of the data strobe signal DSxe2x80x2 that trigger the flip-flop 422 are within the stable portion of the data signal DAT. Hence, the flip-flop 422 is able to latch-up the data precisely.
There are a few types of delay elements. For example, a winding circuit line on a printed circuit board can be used to increase transmission time. Alternatively, passive devices inside an integrated circuit can be used as a delay element. However, both types of delay elements are not so suitable for forming a high efficiency circuit. Winding a long circuit line on a printed circuit board will occupy a large area, and hence will decrease the level of integration. Due to circuit fabrication, the same passive delay elements inside an integrated circuit share different delay time. The maximum delay time in a delay element can be twice the minimum delay time. For example, if the intended delay time of a delay element is Ins, delay time of the actual delay element may vary from 0.67 ns to 2 ns.
The design of delay element is rather difficult because too much or too little delay for the data strobe signal will lead to the interception of inaccurate data. In fact, accuracy of received data depends on whether the amount of delay (Ddsxe2x80x94da) between the data strobe signal DS and the data signal DAT is appropriate. In other words, accuracy depends on whether the rising or falling edge of the data strobe signal DS resides within a stable portion for reading data signal DAT.
Factors that affect the amount of delay Ddsxe2x80x94da between data strobe signal DS and data signal DAT includes: 1. Skew between data strobe signal DS and data signal DAT from the transmission terminal to the receiving terminal (xcfx81s); 2.Delay caused by the delay element (sd). Hence, the amount of total delay Ddsxe2x80x94da between data strobe signal DS and data signal DAT is xcfx81s+sd. Factors that affect signal skew xcfx81s includes: various differences among output buffers, layout on a printed circuit board, threshold voltage of output buffers, setup time and hold time for flip-flops and so on. On the other hand, factors that affect the delay time of a delay element includes: design of the delay element, temperature, humidity, voltage, CPU operating frequency, electromagnetic interference and so on. For example, due to the dynamic influence by various factors, there is a possible delay of between 0.5xcx9c1.8 ns for a 66 Mhz system. Furthermore, the amount of delay is different for different operating frequencies such as 66 Mhz, 75 Mhz, 83 Mhz, 100 Mhz, 133 Mhz and higher. In general, as the operating frequency is increased, clock signal cycle is shortened and tolerable error range is reduced. Whenever the data strobe signal DS is too long or too short, the receiving terminal latches inaccurate data such that the system can not operate normally Moreover, even if an accurate delay value is estimated, the delay value may still vary according to changes in other factors such as temperature, voltage, frequency or electromagnetic interference. Hence, xcfx81s and sd may vary and the calculated value may again fall outside the best margin.
To reduce data loss or system failure, the data strobe signal DS is delayed one quarter cycle of the clock signal cycle CLK no matter what the reference clock frequency is. The delayed data strobe signal DS always starts on the mid-portion of the positive half cycle or negative half cycle of the clock signal CLK. Hence, accurate data is always obtained.
FIG. 5 illustrates a circuit block diagram showing a conventional technique for generating a quarter clock cycle delay.
As shown in FIG. 5, the delay elements 511, 512, 513, 514, the phase detector 520, the counter 530 together constitute a delay lock loop. The delay lock loop can substantially equalize the phase of the signal at the two input terminals I1 and I2 of the phase detector 520. All the delay elements 511, 512, 513, 514 and 515 have identical delay characteristics. In other words, when each delay element is set with the same delay parameter through its control terminal C, each delay element will produce the same amount of signal delay.
By properly selecting delay elements 511, 512, 513 and 514, a signal from the input terminal I1 of the phase detector 520 with the delay lock loop being stabilized is delayed by one cycle of the clock CLK. Because all the delay elements 511, 512, 513 and 514 have identical characteristics, delay time of each delay element is one quarter cycle of a clock signal. The delay element 515 is used to delay the data strobe signal DS on a receiving terminal.
Although the aforementioned method of using a delay lock loop to determine the delay parameters of a delay element can produce an accurate delay time, four delay elements are needed in the delay lock loop. Since each delay element has to occupy a certain area, total area occupation of the delay elements on a silicon chip is large. Moreover, in a modem computer system, several clock frequencies are used. Since each clock frequency requires a set of delay lock loop, all the delay elements on a chip occupy a significant area.
In conclusion, conventional delay element system has the following drawbacks:
1. Delay time controlled by increasing the length of conductive lines is not accurate. Furthermore, long conductive lines occupy a large area on a printed circuit board. Winding circuit lines are not good for multiple frequencies.
2. It is also difficult to control the accuracy of delay time by forming a delay circuit with passive devices. In addition, external factors and different operating frequencies can easily influence the delay time of the delay circuit.
3. Although a delay lock loop can generate desired delay within a range of operating frequencies accurately, devices required for a delay lock loop will occupy a large chip area. To produce a delay circuit for multiple operating frequencies, many additional groups of sub-circuits are needed.
One object of the present invention is to provide a delay device capable of accurately controlling delay time and working in different operating frequencies. In addition, delay is hardly affected by external factors.
A second object of this invention is to provide an inexpensive delay device that occupies a small chip area.
A third object of this invention is to provide a delay device having a delay lock loop capable of calibrating delay time to a precise value.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a delay device having a delay lock loop therein capable of receiving an external input signal and outputting a delayed signal. The delay device comprises a phase detector, a counter and a delay element.
The phase detector has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a complementary signal of a reference signal. The counter has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the phase detector for changing a count value at its output terminal. The delay element has an input terminal, an output terminal and a control terminal. The input terminal receives either the external input signal or the reference signal, the output terminal is coupled to the second input terminal of the phase detector, the output terminal outputs the delayed signal, the control terminal is coupled to the output terminal of the counter, and the counter value determines a pre-defined period between the external input signal and the delayed signal such that the external input signal is delayed by the delay period as the delayed signal output.
In addition, the present invention further provides a method of calibrating a delay parameter. First, a phase detector and a counter are provided, wherein the phase detector has a first input terminal, a second input terminal and an output terminal. A reference signal and a complementary reference signal are then further provided. The reference signal is sent into the delay element to produce a delayed reference signal. The delayed reference signal is transmitted from the delay element to the first input terminal of the phase detector and transmitting the complementary reference signal to the second input terminal of the phase detector. A count value for the counter is then changed according to a output signal on the output terminal of the phase detector; and the delay parameter is obtained according to the counter value while signal phases at the two input terminals of the phase detector become substantially identical. According to one preferred embodiment of this invention, to maintain the delay time of the delay element at a fixed value can be achieved by maintaining the calculated value at the output terminal of the counter.
According to a second preferred embodiment of this invention, the delay time of the delay device is calibrated by changing the state of the selection signal. Hence, the phase detector, the counter, the delay element together form a delay lock loop circuit, such that the phases of the signals at the two input terminals of the phase detector become substantially identical. After the calibration, changing the state of the selection signal is capable of outputting precisely delayed signal for the delay device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and arc intended to provide further explanation of the invention as claimed.